The present invention relates to on-chip misalignment indication, and more particularly to such misalignment indication using misalignment circuit indicators. Even more particularly, the present invention relates to on-chip misalignment indication using misalignment circuit indicators fabricated in layers of an integrated circuit die wherein a current between two contacts varies as resistance between the contacts varies as a function of misalignment.
During fabrication of the integrated circuit die lithographic processes are used to lay down successive circuit layers that together define electronic devices on the integrated circuit die. Misalignment between successive layers of the integrated circuit die is present in all integrated circuit dies to some degree. There is, however, a tolerable amount of misalignment that may exist in any given integrated circuit die before operation of the integrated circuit die is jeopardized. If too much misalignment occurs between successive layers, the electronic devices will not function properly, i.e., will not function with desired specifications, or will prematurely fail.
Prior art approaches to establishing alignment involve the use of targets in a scribe line against which stencil-like masks for each of the layers are compared, and aligned prior to generating the layer using lithographic processes. Once the masks are aligned, exposed portions of the integrated circuit die are exposed, for example, to ultraviolet light, changing their character and thus defining structures in a particular layer. Alignment of the mask is done by a machine to within angstroms of "perfect alignment". ("Perfect alignment" is perfectly in accordance with design.)
Visual observation using inspection hardware is presently used to verify the alignment of layers during and after fabrication. These visual inspection processes, however, are inherently imprecise and difficult to accurately quantify, and therefore improvements in alignment detection are needed.
Because obtaining accurate layer alignment indication or misalignment indication, as the case may be, in heretofore known integrated circuit dies is not possible, reliance must be made on techniques such as burn-in, and ultimately component failure, in order to assess whether significant enough misalignment between layers within an integrated circuit die exists from a performance perspective to cause device malfunction.
Presently, reliance on these visual inspection techniques and/or on indirect in-line measurements of component performance in order to determine whether misalignment is within tolerance is unacceptable. Because these approaches are either inexact, in the case of visual inspection, or indirect, in the case of in-line measurements of component performance, it is currently difficult or impossible to identify integrated circuit dies that contain latent misalignment defects (due to generally small amounts of misalignment), and thus reliable component failure predictions based on misalignment determinations cannot consistently be made.
What is needed is an approach for obtaining very accurate alignment information from an integrated circuit die in process development, product characterization, and in understanding different alignment sensitivities (tolerances). Further, what is needed is an approach in which very accurate quantifiable alignment information is obtained while minimizing the possibility of misinterpretation. An ability to gather large quantities of alignment information and to determine alignment during failure analysis would also be desirable. It also would be highly desirable if an acceptable and quantifiable amount of misalignment (misalignment tolerance) could be determined on an integrated-circuit-die-design-by-integrated-circuit-die-design basis, as opposed to present methods, which determine such misalignment amounts (or tolerances) on a technology-by-technology basis. Detection of misalignment after silicon wafers have been cut into individual dies is extremely difficult and impossible using prior art approaches, other than through failure analysis, however such an ability would be highly desirable. Furthermore, it would be useful to be able to determine misalignment trends in particular alignment hardware or in particular integrated circuit devices, which is not feasible using prior art techniques, because precise quantifiable misalignment data is not available,
The present invention advantageously addresses the above and other needs.